2012年1月27日 · Re: LDO vs Level shifter The main benefit of an LDO over a buck converter is lower noise. However, the efficiency is worse especially for large voltage drops. 12 V to 3.3 V implies an efficiency of 28% for the LDO, vs 80-90% for the buck.

2013年2月18日 · LDO is a linear regulator - the efficiency depends on the actual load but it's much lower than Bucks. LDOs are "quiter" (very low ripple) than switching regulators - therefore they tend to be used in applications that require that - FPGA core voltage supply for example.

LDO when the ESR is too high, and Figure 6 illustrates the LDO frequency response when the ESR is too low . For both cases, the phase margin at UGF is less than or equal to 0¡, resulting in system instability . Figures 5 and 6 show the stable range of Z esr. Since ESR can cause instability , LDO manufacturers

2008年5月18日 · Re: LDO behavior *For transient : You can imagine the pass-element for very fast changes seen as a current source [Ref Dr Millikan paper for cap free ldo](as before EA catch-up the EA output voltage is constant ) & so varying the load can be seen by two points of views :

2005年7月20日 · To eliminate some confusions, perhaps another interpretation of the LDO circuit helps: If you redraw the circuit such that the reference voltage appears as an input - and the voltage Vin as a "disturbing" signal - then indeed the voltage divider factor R2/(R1+R2) acts as a feedback factor.

2019年3月27日 · Hi I am working on a LDO design that requires a rather large PMOS pass transistor due to the specified max current. I have issues with pulling the pass transistor gate high enough at no load conditions to avoid the output voltage creeping upwards due to leakage in the pass transistor. In...

2005年10月21日 · ac analysis of ldo I also confused it, sometimes, I use the AC source with ac=1V to break the loop. sometime, I use the resistor with AC=1G , and a cap=1F . and sometime, I use the ind=1G and a cap =1F. the only diff thing I thought is the phase of it different. But offten, the gain plot is also diff.

2007年4月10日 · The advantages of a NMOS transistor (source follower output) in LDO is that the output capacitance can be very small (few pF) and because of the inherent low impedance at the output, the output need not be a dominant pole.In PMOS pass transistor LDO's, the output has to be generally a dominant pole thus needing a large load cap for being stable.

2006年5月12日 · pmos pass transistor Hi, all I am designing a LDO regulator, the minimal power supply voltage is 4.75V, and the output voltage is 4.5V, the maximum output current is 20mA. In order to assure the pmos pass transistor operating in saturation, I have to set a large W/L, but i can not provide this...

2005年3月28日 · The easiest way to test a LDO's stability is to step the load, up and down. Observe the waveform, and adjust compensation until you see a damped waveform. AC sometime give you good PM, but you may be umdamped or have peakings. But you must always do a sanity check in AC, to determine the location of poles and zeros.