2022年8月17日 · A compute-in-memory neural-network inference accelerator based on resistive random-access memory simultaneously improves energy efficiency, flexibility and accuracy compared with existing...

Compute-in-memory (CIM) is a new computing paradigm that addresses the memory-wall problem in hardware accelerator design for deep learning.

2022年8月18日 · Stanford University engineers have come up with a potential solution: a novel resistive random-access memory (RRAM) chip that does the AI processing within the memory itself, thereby eliminating the separation between the compute and memory units.

2022年8月19日 · To overcome the data movement bottleneck, researchers implemented what is known as compute-in-memory (CIM), a novel chip architecture that performs AI computing directly within memory rather than in separate computing units.

2023年11月13日 · Here, we provide a full-spectrum classification of all CIM technologies by identifying the degree of memory cells participating in the computation as inputs and/or output.

2022年8月17日 · The NeuRRAM chip is not only twice as energy efficient as the state-of-the-art "compute-in-memory" chips, an innovative class of hybrid chips that runs computations in memory, it also...

We designed and experimentally validated an AI inference chip – NeuRRAM [1], that implements brain-like compute-in-memory (CIM) architecture innately using resistive random-access memory (RRAM) [2].

New computing architectures and chip designs that make more intelligent use of new memory technologies are key to unlocking extreme energy efficiency. We push the frontier of compute-in-memory AI chips through co-designs and prototyping.

2022年4月12日 · A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References Abstract: Resistive random access memory (RRAM)-based compute-in-memory (CIM) has shown great potential for accelerating deep neural network (DNN) inference.

2023年8月10日 · Here we report a multicore AIMC chip designed and fabricated in 14 nm complementary metal–oxide–semiconductor technology with backend-integrated phase-change memory. The fully integrated chip...