This paper will describe an approach to verify dynamic clock switching. Figure 1 below shows an example of a clock generation based on clock divider register values. clk_div_sel1 and clk_div_sel2 are ...

The AVR128DA28 that’s used here tops out at 24 MHz (double that if you use the PLL) but [David] got reliable results from his clock divider feeding a signal as high as 90 MHz to the input pin.